As is well known in the microelectronics industry, integrated circuit devices may be susceptible to damage from application of excessive voltages, for example, ESD events. In particular, during an ESD event, charge transferred within a circuit may develop voltages that are large enough to break down insulating films (e.g. gate oxides) on the device or dissipate sufficient energy to cause electrothermal failures in the device. Such failures may include contact spiking, silicon melting, or metal interconnect melting. As such, protection circuits are often connected to Input/Output (I/O) bonding pads of an integrated circuit to safely dissipate energy associated with ESD events away from active circuitry. Protection circuits may also be connected to power supply pads or between power supply buses to prevent damage to active circuitry. In developing effective ESD protection circuitry, circuit designers may, however, be limited with regard to the particular structures used, since the protection circuit will often be closely associated with the remainder of the integrated circuit that it is intended to protect. For instance, integrated circuits which operate with applications of high voltages (e.g., VDD>12V) may include protection circuitry configured to accommodate high voltage levels.
One of the solutions for an ESD protection circuit or ESD clamp is to have a protection-designated high voltage drain extended metal-oxide semiconductor (DEMOS) transistor coupled to the I/O bonding pads or any node to be protected. The DEMOS usually further consists of a silicon-controlled rectifier (SCR) which is triggered/turned on by an ESD zap to provide a low resistant path for the high voltage discharge, thus protecting the node.
FIG. 1 illustrates a cross-sectional view of an ESD clamp 50 incorporating a SCR circuit 52 of an example of such circuits. Referring to FIG. 1, the characteristic P-N-P-N structure of SCR circuit 52 is formed by the P+ region, the N-well/Deep N-well, the P-substrate and the N+ source. In one embodiment, P+ region is coupled to the protected node and the N+ source is coupled to a voltage low node or a ground node. During an ESD event, the SCR circuit 52 is triggered to drain the current associated with the ESD zap in order to protect the node. It is imperative to state that ESD clamp 50 is one of many embodiments of ESD protection circuit incorporating SCR.
FIG. 2 illustrates a plot of current as a function of voltage of an ESD device incorporating SCR such as ESD clamp 50. When the ESD device is used for ESD protection, the N+ drain and P+ contact region are connected to the Vdd power pad or the node to be protected. While the gate, the N+ source, and the P+ collection region are all tied together and connected to a Vss ground pad, thus turning the DEMOS off as a transistor. Referring to FIG. 2, curve A represents a response to a first ESD event for an ESD device incorporating SCR such as ESD clamp 50. In an embodiment, curve A may also represent the response to subsequent ESD events. During regular operation, the current going through ESD device 50 is very minimal as the device is off (gate connected to a ground pad). However, during an ESD zap, when the supply voltage reaches/exceeds the trigger voltage of ESD device 50, SCR 52 is turned on and starts to conduct and provide a discharging path to drain current associated with the ESD zap in order to protect the node and the circuit it is connected. Subsequent to the turn on of the SCR 52, the device will experience a snapback to a holding voltage, which is much lower than the trigger voltage. In this stage, the ESD device 50 will provide an extremely low impedance discharging path to supply voltage (latch on). In the event that the holding voltage is lower than the supply voltage in regular operational conditions, SCR 52 and ESD device 50 may remain “on” and continue to provide a low impedance discharging path to drain current even after the ESD event. In one embodiment, this ESD false-triggering phenomenon will lead to permanent damages to ESD device 50. Referring still to FIG. 2, Curve B represents a leakage current of ESD device 50 associated with ESD events described in Curve A. After each ESD event, the leakage current, specifically at 36V for Curve B, is measured and monitored to determine if ESD device 50 is damaged.
The main challenge is to design an ESD device that has a high holding voltage such that the ESD device will be back to the “off” state after an ESD event to sustain protection to the node.